1. Field of the Invention
This invention relates to improvements in integrated circuit isolation techniques and apparatus, and more particularly to improvements in apparatuses and methods for galvanically isolating two circuits, such as integrated circuits, or the like, from each other.
2. Relevant Background
In many circuit constructions, it is often necessary to provide dc isolation between two or more integrated circuits. For example, not uncommonly, the ground potential of one integrated circuit may be at a different dc level than a ground potential of another integrated circuit to which it may be connected. When such ground potential isolation is needed, typical ground isolating schemes have been employed. One such scheme, for example, is that described by IEEE 1394-1995, Annex J.
In the past, however, when isolated ground design circuits such as those specified by IEEE 1394-1995 have been required, the current isolation scheme between the physical layer device and the link layer device suggested in the IEEE standard is costly in terms of external components required, board space, supply current, and silicon area. It also does not have good noise margin or propagation delay.
More particularly, one of the problems with the prior art techniques of providing isolation between two integrated circuit devices is the large number of required components needed to effect the dc isolation between pins. For example, the IEEE 1394-1995 standard requires, in its capacitor embodiment, two relatively large-sized capacitors and seven resistors off-device as well as specific differentiating, tristating, and hysteresis input buffer circuitry on-device. Thus, it can be seen that when the required isolation circuitry is employed over a number of interconnections for every pin on each integrated circuit that is interconnected, a large number of such isolation circuits will be required. Moreover, depending upon the voltages that are to be handled by the capacitors, for example, about 50 volts, or less, relatively large size capacitors are needed consuming even more space on the board through which the interconnect is accomplished. Furthermore, it will be appreciated, of course, that accompanying the large number of components required to accomplish the integrated circuit interface and isolation, is a concomitant increase in the cost of the final product.
The IEEE 1394-1995 standard additionally has an isolation circuit embodiment that is implemented with a transformer. The transformer isolation circuit embodiment also requires a large number of components, but can be constructed to withstand higher dc voltages than the capacitor embodiment, for example, about 500 volts, or less. Again, the transformer embodiment requires a significant amount of interconnect physical area in which to construct the isolation circuit and, when multiplied by the number of pins that are interconnected, a significant amount of circuit components and layout area is consumed.
In typical operation of a circuit that is interconnected using isolation circuitry of the type generally used in accordance with the IEEE 1394-1995 standard to enable bi-directional signals to be delivered to and supplied from the integrated circuit, a differentiating output buffer circuit and a digital input buffer having signal hysteresis are provided. The output buffer and input buffer are generally connected to the same input/output pin, to achieve bi-directional signal transfer. The output buffer circuit is generally clocked by clock pulse sources onboard the integrated circuit device on which the output buffer is constructed.
Differentiation circuits of the type provided as a part of the input buffer circuit are difficult and complex to construct in an integrated circuit structure and, additionally, require considerable "real estate" on the integrated circuit device. When the number of input/output pins is increased, an increased amount of "real estate" on the integrated circuit device is required to provide the multiplied number of differentiating circuits for each input buffer's section.
Moreover, as mentioned, the differentiation input buffer circuit typically has an amplifier having hysteresis. The hysteresis requires a received signal transitioning from low to high exceed a particular level, for instance, above 1/2 V.sub.DD, and which, on the other hand, requires a signal transitioning from high to low to be less than 1/2 V.sub.DD to turn off the detector circuit.
Thus, in normal operation, if an input signal applied to the circuit is of general magnitude of about 1/2 V.sub.DD, if the input circuit is constructed of a typical CMOS inverter, commonly both of the transistors of the inverter may be biased to conduct. This results in a relatively large current drawn through the device. When the current draw is multiplied across all the input/output pins of the integrated circuit device, it can be appreciated that a relatively large current is required in the quiescent state of the integrated circuit device. This can be disadvantageous in many applications, such as video cameras/camcorders, lap top computers, and the like, which are battery operated, and which require minimal use of the battery capacity for extended operation.
Typically in the operation of the isolation circuit between two integrated circuits in delivering a signal from one integrated circuit device to another, if, for example, an output pulse is to be delivered extending beyond a single clock pulse, a high state is clocked from the output buffer of one integrated circuit at the a clock pulse output. Thereafter, the output of the output buffer is tristated, or switched to a high impedance state. The signal is detected by the input buffer circuit of the other integrated circuit, which switches to a high state. By virtue of the hysteresis effect of the input buffer circuit, the input buffer continues to report that a high state is being received, until the input signal drops below the threshold value, below 1/2 V.sub.DD, for example, as explained above.
Another of the problems that has been experienced with isolation circuits in the past is that typically isolation circuits have a limited noise immunity. In particular, isolation circuits do not generally permit a large margin of noise immunity because of the design requirement for an amount of hysteresis in the input buffer circuit. As a result, for example, if an input voltage is 1/2 V.sub.DD at an input pin, the difference is very small between the input potential and the threshold potential that must be exceeded for the circuit to change states. (The input would typically be at 1/2 V.sub.DD since the output of the transmitter or output buffer portion of the integrated circuit to which the circuit is connected is typically in a tristate impedance.) Consequently, if a noise spike or pulse is induced onto the input line, the magnitude of the pulse necessary to reach the switching threshold of the input buffer circuit is relatively small. A typical isolation circuit, for example, may provide noise immunity of only about 0.2 volts to about 0.8 volts, depending upon the particular variables of the circuit.
Another consideration in the design of the device interface circuits constructed according to the IEEE 1394-1995 standard, is that of the propagation delay through the interface circuit. Typically, in the past, the propagation delay that is experienced is about two to three nanoseconds. In many applications, this propagation delay at least may need to be considered, and at worst, may disqualify the circuit for the particular application considered.
What is needed, therefore, is a method and apparatus for providing a circuit and method for isolating dc or galvanic voltage between two or more circuits, such as integrated circuits, or the like.